Overview
Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all products.
Responsibilities
ASIC design engineer responsible for the design, verification, and evaluation of digital circuits in high speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. The successful candidate will be responsible for block and /or chip level verification.
Qualifications
MSEE with 8+ years of experience.
Fundamental concepts in digital logic design.
Understand ASIC verification flows and methodologies.
Verilog and SystemVerilog/SystemC/Vera.
Improve the design methodology and flow.
Design verification for various type of SerDes IPs ranging from 10Gbps to 224Gbps data-rates for different applications.
Collaborate with Analog/DSP/Digital Design/FW/AE teams to deliver the competitive SerDes IP solutions for all product lines.
Provide the support to the product teams, for both pre and post silicon.
Good personal communication skills and team working spirit.
Fundamental concepts in digital logic design.
Strong Perl and Tcl scripting
UNIX Shell scripting (Csh, Bash)
Formal verification
Low power design
MATLAB and C/C++ based system simulation and evaluation
DSP function hardware implementation knowledge
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